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ISL45041
Data Sheet August 29, 2006 FN6189.2
TFT-LCD I2C Programmable VCOM Calibrator
The VCOM voltage of an LCD panel needs to be adjusted to remove flicker. This part provides a digital interface to control the sink-current output that attaches to an external voltage divider. The increase in output sink current lowers the voltage on the external divider, which is applied to an external VCOM buffer amplifier. The desired VCOM setting is loaded from an external source via a standard 2-wire I2C serial interface. At power up the part automatically comes up at the last programmed EEPROM setting. An external resistor attaches to the SET pin, and sets the full-scale sink current that determines the lowest voltage of the external voltage divider. The ISL45041 is available in an 8 Ld 3mmx3mm TDFN package with a maximum thickness of 0.8mm for ultra thin LCD panel design. An evaluation kit complete with software to control the DCP from a computer is available. Reference Application note AN1207 and Ordering Information.
Features
* 128-Step Adjustable Sink Current Output * 2.25V to 3.3V Logic Supply Voltage Operating Range (2.25V Minimum Programming Voltage) * Analog Supply Voltage Range 4.5V to 18V for VDD from 2.6V to 3.6V; 4.5V to 13V for VDD from 2.25V to 2.6V * I2C Interface (Slave and Transmitter) - Address: 1001111 * On-Board 7-Bit EEPROM * Output Adjustment SET Pin * Output Guaranteed Monotonic Over-Temperature * Thin 8 Ld 3mmx3mm DFN (0.8mm max) * Pb-free available (RoHS compliant)
Applications
* LCD Panels
Pinout
ISL45041 (8 LD TDFN) TOP VIEW
OUT 1 AVDD 2 WP 3 GND 4 8 7 6 5 SET SCL SDA VDD
Ordering Information
PART NUMBER (Note) ISL45041IRZ ISL45041IRZ-T* TEMP. RANGE PART MARKING (C) 041Z 041Z PACKAGE (Pb-Free) PKG. DWG. #
0 to +85 8 Ld 3x3 TDFN L8.3X3A 0 to +85 8 Ld 3x3 TDFN L8.3X3A Tape and Reel
ISL45041EVAL1Z Evaluation Board *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL45041 Pin Descriptions
PIN OUT TYPE Output PULL U/D FUNCTION Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 128. See SET pin function description for the maximum adjustable sink current setting. High-Voltage Analog Supply. Bypass to GND with 0.1F capacitor. Pull-Down Write Protect. Active Low. To enable programming, connect to 0.7*VDD supply or greater. Ground connection. System power supply input. Bypass to GND with 0.1F capacitor. I2C Serial Data Input I2C Clock Input Maximum Sink Current Adjustment Point. Connect a resistor from SET to GND to set the maximum adjustable sink current of the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET.
AVDD WP GND VDD SDA SCL SET
Supply Input Supply Supply In/Out Input Analog
Block Diagram
ISL45041
AVDD
SCL D<7:0> SDA I2C INTERFACE DATA REGISTERS 128 ANALOG DCP AND CURRENT OUTPUT BLOCK
IOUT
SET
WP 7-BIT EEPROM
GND
VDD
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FN6189.2 August 29, 2006
ISL45041
Absolute Maximum Ratings
VDD to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4V Input Voltages to GND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +4V AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V Output Voltages to GND OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20V ESD Rating HBM for Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV HBM for Input Pins (SCL, SDA) . . . . . . . . . . . . . . . . . . . . . . . .4kV
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (C/W)
8 Ld TDFN Package. . . . . . . . . . . . . . . . . . . . . . . . . 170 Moisture Sensitivity (see Technical Brief TB363) All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2 Maximum Junction Temperature (Plastic Package) . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range ISL45041IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9k; Unless Otherwise Specified. Typicals are at TA = +25C SYMBOL TEST CONDITIONS TEMP (C) MIN (Note 7) TYP MAX (Note 7) UNITS
PARAMETER DC CHARACTERISTICS VDD Supply Range - Operating VDD Supply Range - EEPROM Programming VDD Supply Current AVDD Supply Range
VDD VDD IDD AVDD (Note 4) VDD Range 2.6V to 3.6V VDD Range 2.25V to 2.6V
Full Full Full Full Full Full Full Monotonic Over-Temperature Full Full Full Through RSET (Note 5) To GND, AVDD = 20V To GND, AVDD = 4.5V Full Full Full Full Full Full (Note 3) 25 to 55 Full Full (Note 3) Full Full @ 3mA @ 3mA Full Full
2.25 2.25 4.5 4.5 7 10 2.25 VSET + 0.5V 0.7*VDD 15 0.4 -
7 20 1:20 8 <10 0.22*VDD 25 -
3.6 3.6 50 18 13 25 7 1 2 8 200 45 13 0.3*VDD 35 0.4
V V A V V A Bits LSB LSB LSB A k k V/V s V mV V V V A V V
AVDD Supply Current SET Voltage Resolution SET Differential Nonlinearity SET Zero-Scale Error SET Full-Scale Error SET Current SET External Resistance
IAVDD SETVR SETDN SETZSE SETFSE ISET SETER
(Note 2)
AVDD to SET Voltage Attenuation OUT Settling Time OUT Voltage Range SET Voltage Drift SDA, SCL, WP Input Logic High SDA, SCL, WP Input Logic High SDA, SCL, WP Hysteresis WP IL SDA, SCL Output Logic High SDA, SCL Output Logic Low
AVDD to SET OUTST VOUT SETVD VIH VIL
(Note 3) to 0.5 LSB Error Band (Note 3)
ILWPN VOHS VOLS
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FN6189.2 August 29, 2006
ISL45041
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 10V, OUT = 5V, RSET = 24.9k; Unless Otherwise Specified. Typicals are at TA = +25C (Continued) SYMBOL TEST CONDITIONS TEMP (C) MIN (Note 7) TYP MAX (Note 7) UNITS
PARAMETER I2C SCL Clock Frequency I2C Clock High Time I2C Clock Low Time I2C Spike Rejection Filter Pulse Width I2C Data Set-up Time I2C Data Hold Time I2C SDA, SCL Input Rise Time I2C SDA, SCL Input Fall Time I2C Bus Free Time Between Stop and Start I2C Repeated Start Condition Set-up I2C Repeated Start Condition Hold I2C Stop Condition Set-up I2C Bus Capacitive Load Capacitance on SDA Capacitance on SCL
FSCL tSCH tSCL tDSP tSDS tSDH tICR tICF tBUF tSTS tSTH tSPS Cb CSDA CS WP = 0 WP = 1 Dependent on Load (Note 6) (Note 6)
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
0 0.6 1.3 0 100 0 1.3 0.6 0.6 0.6 -
20 + 0.1*Cb 20 + 0.1*Cb -
400 50 900 1000 300 400 10 10 22 100
kHz s s ns ns ns ns ns s s s s pF pF pF pF ms
Write Cycle Time NOTES: 2. Tested at AVDD = 20V.
tW
Full
-
3. Simulated and Determined via Design and NOT Directly Tested. 4. Simulated Maximum Current Draw when Programming EEPROM is 23mA, should be considered when designing Power Supply. 5. A Typical Current of 20A is Calculated using the AVDD = 10V and RSET = 24.9k. Reference "RSET Resistor" on page 5. 6. Simulated and Designed According to I2C Specifications. 7. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested.
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FN6189.2 August 29, 2006
ISL45041 Application Information
This device provides the ability to reduce the flicker of an LCD panel by adjustment of the VCOM voltage during production test and alignment. A 128-step resolution is provided under digital control, which adjusts the sink current of the output. The output is connected to an external voltage divider, so that the device will have the capability to reduce the voltage on the output by increasing the output sink current.
AVDD ISL45041 OUT RSET ISET R2 AVDD R1 +
RSET Resistor
The external RSET resistor sets the full-scale sink current that determines the lowest voltage of the external voltage divider R1 and R2 (Figure 1). The voltage difference between the VOUT pin and ISET pin (Figure 2) has to be greater than 1.75V. This will keep the output MOS transistor in the saturation region. Expected current settings and 7-Bit accuracy occurs when the output MOS transistor is operating in the saturation region. Figure 2 shows the internal connection for the output MOS transistor. The value of the AVDD supply sets the voltage at the source of the output transistor. This voltage is equal to (Setting/128) x (AVDD/20). The ISET current is therefore equal to (Setting/128) x (AVDD/20 x RSET). The value of the Drain voltage is found using Equation 2. The values of R1 and R2 (Equation 2) should be determined (setting equal to 128) so the minimum value of VOUT is greater than 1.75V + AVDD/20.
AV SETTING DD ----------------------------x ----------------128 20 VOUT PIN AVDD = 15V R1 R2
SET
FIGURE 1. OUTPUT CONNECTION CIRCUIT EXAMPLE
The adjustment of the output is provided by the 2-wire I2C serial interface.
Expected Output Voltage
The ISL45041 provides an output sink current, which lowers the voltage on the external voltage divider (VCOM output voltage). Equation 1 and Equation 2 can be used to calculate the output current (IOUT) and output voltage (VOUT) values.
AV DD Setting I OUT = -------------------- x -------------------------20 ( R SET ) 128 R1 R2 Setting V OUT = -------------------- AV DD 1 - -------------------- x -------------------------- 20 ( R SET ) 128 R 1 + R 2 NOTE: Where setting is an integer between 1 and 128. (EQ. 1)
AVDD
VSAT 0.5V RSET
ISET PIN
FIGURE 2. OUTPUT CONNECTION CIRCUIT EXAMPLE
Ramp-Up of the VDD Power Supply
It is required that the ramp-up from 10% VDD to 90% VDD level be achieved in less than or equal to 10ms to assure that the EEPROM and Power-on-reset circuits are synchronized and the correct value is read from the EEPROM Memory.
(EQ. 2)
Table 1 gives the calculated value of VOUT for the evaluation board using the on-board resistors values of: RSET = 24.9k, R1 = 200k, R2 = 243k, and AVDD = 10V.
TABLE 1. SETTING VALUE 1 10 20 30 40 50 60 70 80 90 100 110 128 VOUT 5.468 5.313 5.141 4.969 4.797 4.625 4.453 4.281 4.109 3.936 3.764 3.592 3.282
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FN6189.2 August 29, 2006
I2C Timing Diagram
Figure 3 shows the I2C timing diagram and expected scope photos of SCL and SDA when writing all zeros or all ones.
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7-BIT ADDRESS
9
F
0 TO WRITE TO EEPROM 8-BIT ADDRESS
I2C Slave Address
E
6
ISL45041
FN6189.2 August 29, 2006
FIGURE 3. ISL45041 I2C TIMING DIAGRAM
ISL45041 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.15 C A A D 2X 0.15 C B
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 MIN 0.70 NOMINAL 0.75 0.02 0.20 REF 0.25 0.30 3.00 BSC 2.20 2.30 3.00 BSC 1.40 1.50 0.65 BSC 0.25 0.20 0.30 8 4 0.40 1.60 2.40 0.35 MAX 0.80 0.05 NOTES 5, 8 7, 8, 9 7, 8, 9 8 2 3 Rev. 3 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals.
E 6 INDEX AREA TOP VIEW B
A3 b D D2 E
// 0.10 C 0.08 C
E2 e k L N Nd
A C SEATING PLANE
SIDE VIEW
A3
D2 (DATUM B) 1 2 D2/2
7
8
6 INDEX AREA (DATUM A)
NX k E2 E2/2
3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
NX L N 8 N-1 e 5 (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" TERMINAL TIP FOR EVEN TERMINAL/SIDE e (A1) L1 10 L 0.10 M C A B NX b
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-WEEC-2 except for the "L" min dimension.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 7
FN6189.2 August 29, 2006

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